There are many integrated circuits (IC) chip, or die, packaging technologies. Ultra-small form factor package assemblies seek to minimize package assembly thickness or “z-height”. In some applications (e.g., mobile devices), the package assembly thickness is one of the most important parameters in response to the design trend toward thinner devices. However, reduced IC chip thicknesses desirable for ultra-small form factor applications are associated with increased thermal dissipation. Demand for ICs to be functioning at high temperature (e.g., 125 C or higher) is also making package assembly thermal management more challenging.
Conventional techniques to improve IC thermal dissipation for molded IC packages include exposed-die molding where the back surface of the IC chip (opposite the circuitry) is not enclosed by the mold compound. While this technique allows an IC chip to be somewhat thicker than it could otherwise, or allows for application of a thermal interface material (TIM) and attachment of an integrated heat spreader (IHS), such package assembly thicknesses can exceed 300 μm, making them unsuitable for ultra-small form factor applications.